CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
User’s Manual U15905EJ2V1UD
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(b) Setting these registers as compare registers (CMSn0 and CMSn1 of TMCn1 = 1)
When these registers are set as compare registers, the TMn and register values are compared for each
count clock, and an interrupt is generated by a match. If the CCLRn bit of timer mode control register n1
(TMCn1) is set (1), the TMn value is cleared (0) at the same time as a match with the CCn0 register (it is
not cleared (0) by a match with the CCn1 register) (n = 0, 1).
Compare registers are equipped with a set/reset function. The corresponding timer output (TOn) is set or
reset, in synchronization with the generation of a match signal (n = 0, 1).
The interrupt selection source differs according to the function of the selected register.
Cautions 1. When writing to capture/compare registers n0 and n1, always set the TMCAEn bit to 1
first. If the TMCAEn bit is 0, the data that is written will be invalid.
2. Write to capture/compare registers n0 and n1 after setting them as compare registers
via TMCn0 and TMCn1 register settings. If they are set as capture registers (CMSn0
and CMSn1 bits of TMCn1 register = 0), no data is written even if a write operation is
performed to CCn0 and CCn1.
3. When these registers are set as compare registers, INTPn0 and INTPn1 cannot be
used (n = 0, 1).
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